1. Field of the Invention
The present invention relates to an oscillator with an oscillation circuit such as a crystal oscillation element which can reduce the power consumption of the oscillation circuit and reduce the occurrence of noise to prevent deterioration in oscillation property. It also relates to a clock generator, a semiconductor device and an electronic device incorporating such an oscillator. The electronic device is, for example, a wrist watch, a mobile phone, a personal digital assistance (PDA), or a computer terminal.
2. Description of the Prior Art
Such an electronic device often includes a crystal oscillator. For example, Japanese Patent Application Publication No. 2006-121477 (Reference 1) discloses, as shown in FIG. 8A, a crystal oscillator which includes an inverter circuit 84 which receives the output amplitude of a crystal oscillation circuit 81 to change in output pulse width in accordance with a change in the output amplitude. Thereby, it can detect the amplitude of an oscillation signal of the oscillation circuit 81 by monitoring the pulse width or duty ratio of a pulse signal from the inverter circuit 84, and control the drive voltage VOSC of the oscillation circuit 81 on the basis of a detected result so that the output amplitude thereof is almost turned to a saturation level. It aims to automatically secure, with a simple configuration, an optimal oscillation allowance in line with a difference in products, ambient environment or the level of oscillation at power-on while reducing power consumption during stationary oscillation.
Specifically, the oscillator includes an amplitude detector 82 having the inverter circuit 84, a level converter circuit 85, and a lowpass filter 86, a transformer circuit 83 having a differential amplifier 87 and a PMOS transistor 88, and a stabilizing capacitance 89. The level converter circuit 85 converts the pulse amplitude of the inverter circuit 84 and the low pass filter 86 acquires an integrated value thereof. The integrated value and a reference voltage VREF slightly lower than the output level in amplitude saturation are input to the differential amplifier 87. If the output (integrated value) of the inverter circuit 84 is lower than the reference voltage VREF, the voltage of the gate of the PMOS transistor 88 is decreased to increase the drive voltage VOSC and output amplitude of the crystal oscillation circuit 81. If it is higher than the reference voltage VREF, the voltage of the gate of the PMOS transistor 88 is increased to decrease the drive voltage VOSC and output amplitude of the crystal oscillation circuit 81.
As shown in FIG. 8B, the crystal oscillation circuit 81 in general includes an inverter CI having an enhancement P-channel MOS transistor Qp and an enhancement N-channel MOS transistor Qn, a crystal oscillation element X, load capacitances CG, CD, and a feedback resistance RF. The oscillation circuit 8 outputs an oscillation signal SO.
According to the oscillator disclosed in Reference 1 the oscillation signal SO is output from the crystal oscillation circuit 81 to the inverter circuit 84 of the amplitude detector 82.
The inverter circuit 84 includes a PMOS transistor and an NMOS transistor connected in series between the power supply voltage VOSC and a GND voltage. The oscillation signal is input to the common gate of the two transistors and output from a connecting point of the two transistors.
In this configuration, as long as the input signal has either the power supply voltage VOSC or GND voltage, current does not flow into the inverter circuit 84. However, when it has an intermediate potential simultaneously turning on both the transistors, feedthrough current flows into the inverter circuit 84.
The oscillation signal SO of the oscillation circuit 81 is generally a sine wave and mostly in an intermediate potential between the power supply voltage VOSC and GND voltage. Receiving such a sine wave at the inverter circuit 84 as a logic circuit, feedthrough current flows into the inverter circuit 84 intermittently or inconstantly in a sine wave cycle, which may lead to extraneous power consumption.
Furthermore, the intermittent or inconstant power consumption may cause periodic noise in the power supply voltage VOSC of the oscillation circuit 81, which is likely to adversely affect the oscillation property of the oscillator, especially a deterioration in the jitter characteristics of the oscillation signal.
Further, the inverter circuit 84 outputs a pulse signal with a rectangular sine wave between the voltage VOSC of the oscillation circuit and GND voltage. The pulse signal falls and rises fast and contains high frequency components, and due to its high amplitude, it is likely to cause parasitic capacitive coupling or electromagnetic coupling in the wires of the oscillator, resulting in noise in the voltage VOSC.
Reference 1 does not describe the level converter 85 in detail but it has to convert the output signal from the inverter circuit 84 into a level signal via a logic gate element or a switch element.
Thus, to mount such a logic circuit outputting a rectangular wave pulse signal and analog circuits as the oscillation circuit 81 and transformer circuit 83 on the same semiconductor circuit board, the layout of the elements need be carefully designed to prevent noise with advanced technical know-how. Because of this, there is a problem that development period and product performance are often in a tradeoff relation.
FIG. 9 schematically shows the structure of an oscillator disclosed in Japanese Patent No. 3136600 (Reference 2).
The oscillator in FIG. 9 includes an oscillation circuit 91, a level detector 92 to detect the amplitude level of an oscillation signal SO output from the oscillation circuit 91 and output a rectangular wave pulse signal SP to a switched capacitor 90, a reference voltage generator (frequency-voltage converter) 93, and an amplifier 94 to amplify a reference voltage VREF to supply it to the oscillation circuit 91 as a power supply voltage ED.
In this oscillator, upon receiving the oscillation signal from the oscillation circuit 91, the level detector 92 generates a pulse signal SP to operate an inverter circuit 99, a discharge switch 95 and a bypass switch 96 constituting the switched capacitor 90.
As the one in Reference 1, the oscillator disclosed in Reference 2 uses the logic gate circuits and switches generating rectangular sine wave signals so that it faces the same problem with increasing consumption current due to the feedthrough current and deteriorating the oscillation property due to noise.
Further, Japanese Patent Application Publication No. 2-94803 (Reference 3) discloses an oscillation circuit by use of a peak voltage. It includes an oscillation element, an amplifier supplied with the output of the oscillation element, a peak detector to detect the output peak level of the amplifier, a capacitor charged with the output of the peak detector and discharged with a constant current source, a smoothening circuit to smooth a voltage varying with the charge/discharge of the capacitor, and a comparator to compare the output of the smoothing circuit with a reference level. The gain of the amplifier is controlled in accordance with a result of the comparison by the comparator.
The oscillation circuit in Reference 3 aims to improve distortion in oscillation output waveform and the stability of a solid oscillation element not to shift into a high-order oscillation mode. However, it cannot lower the power supply voltage by just controlling the gain of the oscillation circuit and the oscillation circuit in FIG. 4 thereof is not configured to control the power supply voltage Vcc. Therefore, Reference 3 fails to consider the optimal control over the power supply voltage Vcc and current consumption so that they are to be minimal.
No oscillation technique for solving all the problems above as extraneous power consumption due to transient feedthrough current, deterioration in oscillation property due to noise, especially, jitter characteristics has been proposed. Further, any of References 1 to 3 fail to address the reduction in extraneous power consumption owing to the feedthrough current as described above.